Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the designer describes a module in terms of signals that are generated and propagated through combinatorial modules, from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher-level modules.
When ICs are designed at a higher level, lower level representations are needed before a design can be fabricated or implemented on hardware. For example, if a design is to be implemented on a programmable logic device (PLD), the process to translate the design into an executable form includes synthesis, mapping, placement, routing, and bitstream generation.
An HDL design is synthesized to create a logical network list (netlist), which can be implemented within a particular programmable logic device. Before an HDL design can be synthesized into a netlist, the design must go through the preparatory processes of analysis and elaboration. In the analysis process, the HDL design is examined to determine if it contains syntax or semantic errors. If no errors are discovered, the analyzer creates an intermediate representation of each design module and stores the intermediate representations in a library.
In the elaboration process, the design is reduced to a collection of signals and processes. Each logic component is constructed and connections between logic components are established. This is generally done by parsing the design. For each instance of a design module encountered during parsing, a data structure is created for the instance and placed into a parse tree. The data structure implementing an instance contains the processes of the module, variables used by those processes, and variables representing input and output signals from the module instance. Memory is allocated to store the processes and signal variables and initial values that are assigned to the signal variables. The location or offset of the allocated memory is stored within the data structures.
Following elaboration, executable simulation code is synthesized from the process data files, which are stored in a process library, using the memory addresses and initial values allocated and assigned to the module instances. For each process, a hardware component is selected to implement the process in hardware. Hardware components are selected for each process by either instantiation or inference.
Instantiation and inference are two different methods of adding components to an implemented design. When a component is instantiated, a specific hardware component is identified by a designer to be included in the implementation of the realized design. Instantiation gives a designer full control over how the component is used; therefore, a designer knows exactly how the logic components will be implemented. However, instantiation is not flexible. Generally, in an HDL file, specific syntax must be used to instantiate a component. Therefore, HDL code written to instantiate a component available on a particular field programmable gate array (FPGA) may not be portable to another FPGA if the FPGA does not implement the particular combination of instantiated components.
When a component is inferred, a designer provides a behavioral description of the function to be performed, such as an HDL description. The synthesis tool then interprets the HDL code to determine which hardware components to use to perform the function. Inference offers readable and portable code that can be used to target different architectures. It is often preferable to behaviorally describe the design and let the synthesis tool do the mapping of the code into the gates available in a target programmable logic device. In addition to making the code more portable, all inferred logic is visible to the synthesis tool, allowing the tool to perform optimizations between functions. These optimizations can include logic replications, restructuring and merging, or retiming to balance logic delay between registers.
When device library cells are instantiated, synthesis tools do not optimize them by default. Even when instructed to optimize the device library cells, synthesis tools generally cannot perform the same level of optimization that can be performed at the RTL. Therefore, synthesis tools typically only perform optimizations on the paths to and from these cells, but not through the cells.
There are, however, cases where instantiation is desirable. This is typically when the synthesis tool mapping does not meet the timing, power, or area constraints, or if a particular feature within an FPGA cannot be inferred. With instantiation, the designer has total control over the synthesis tool. For instance, to achieve better performance, the designer can implement a comparator using only lookup tables (LUTs), instead of the combination of LUTs and carry chain elements usually chosen by the synthesis tool. In other instances, instantiation is the only way to make use of the complex resources available in the device. For example, when an Intellectual Property (IP) core is included as part of the design, the source code is not available to allow inference. When an IP core is used, the component must be instantiated using a HDL black box module provided by the IP core vender.
Current methods of inference are performed at the logical level during synthesis. This is done by creating an exhaustive description file of the various patterns for each configuration or combination of logic that may be implemented within each component. When a component has many configurable features, such as the various configurations provided by a multiply-accumulator, the number of patterns needed for inference can become large. As new features are added to the component, new sets of inference patterns must also be created. Additionally, because inference is performed at the logical level, it is impossible to consider and implement timing optimizations
The present invention may address one or more of the above issues.